`timescale 1ns / 100ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/08/17 01:29:53
// Design Name: 
// Module Name: mcu_test
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mcu_test;

reg rstn;
reg clk;

wire ledn;
wire [7:0] gpio;
wire [15:0] bus_din_data;
wire uart_tx;
reg uart_rx;

mcu_top mcu_inst(
    .rstn(rstn),
    .clk_50MHZ(clk),
    .ledn(ledn),
    .gpio(gpio),
    .motor(),
    .uart_tx(uart_tx),
    .uart_rx(uart_rx)
    //.bus_din_data(bus_din_data)
);

pullup(uart_tx);

genvar i;

//generate begin : bus_din_gen
//    for (i = 0; i < 16; i=i+1) begin
//        pullup(bus_din_data[i]);
//    end
//end endgenerate

wire [15:0] pc = mcu_inst.mcu_cpu_inst.pc;

initial begin
    #0 clk <= 0;
    #0 rstn <= 1;
    #1 rstn <= 0;
    #1 rstn <= 1;
end

initial begin
    uart_rx <= 1;
    wait(mcu_inst.locked);
    forever begin
        #10000;
        #8680 uart_rx <= 0;
        #8680 uart_rx <= 0;
        #8680 uart_rx <= 1;
        #8680 uart_rx <= 0;
        #8680 uart_rx <= 1;
        #8680 uart_rx <= 0;
        #8680 uart_rx <= 1;
        #8680 uart_rx <= 0;
        #8680 uart_rx <= 1;
        #8680 uart_rx <= 1;
    end
end

always begin
    #10 clk <= 1;
    #10 clk <= 0;
end

endmodule
